Semiconductor integrated circuits (ICs) are typically designed and fabricated by preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to perform a particular logical function. The schematic diagram or HDL specification is synthesized into cells of a particular cell library. Each cell corresponds to a logical function unit, which is implemented by one or more transistors or other devices. A series of computer-aided design tools generate a netlist of the selected cells and the interconnections between the cells. The netlist is used by a floor-planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. Once the selected cells have been placed and routed, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition, which is used to fabricate the integrated circuit.
During various stages of the design process, verification tools are used to verify different aspects of the design, such as the logic or analog function, the timing, and adherence to certain design rules. One measure of the performance of an IC is expressed by the time delays within the circuit, such as propagation delays, setup delays and hold delays. Propagation delays include the time required for a signal to travel from one location to another, such as from the input of a cell to the output of the cell. A setup delay is the time duration that a signal must be available at an input to a cell prior to a respective clock or other signal transition. A hold delay is the time duration that a signal must be stable after a respective clock or other signal transition.
A worst case setup violation refers to a violation that occurs at a cell input assuming that the signal path leading to that input has a worst case (maximum) delay over variations in process, voltage and temperature. A best case hold violation refers to a violation that occurs at a cell input assuming that the signal path leading to that input has a best case (minimum) delay over variations in process, voltage and temperature.
Since setup violations traditionally have been more difficult to solve than hold violations, the adjustment and repair of best case hold violations within the design process have largely become an afterthought. Hold violations are often ignored until after much of the functional verification and setup violations have been fixed. Because of this, designers often look for a minimal-effort approach.
Upon completion of cell placement, design verification and the correction of the bulk of the existing setup violations, the designer finally broaches the issue of best case hold violations. The approach the designer implements to fix these violations may often be incorporated in what can be described as an “Industry Standard Method”. This method indiscriminately inserts a buffer at the input pin of the violating storage element, such as a flip-flop or memory. The method is usually implemented via manually-created Engineering Change Order (ECO) files based on the violations reported through a Static Timing Analysis (STA) tool.
The Industry Standard Method introduces a myriad of issues, including:
1. Manual identification of end point storage elements reported by the STA tool is a time consuming effort;
2. Generating ECOs without an intelligent systematic approach may create more setup violations than the number of hold violations at the beginning of the process;
3. Designers will typically attempt to minimize effort by selecting one generic buffer to solve a wide range of violations causing unnecessary iterations and possible new setup violations; and
4. By causing new setup and/or hold violations, the designer is forced to attempt to fix problems interactively in a “ping-pong” fashion.
For example, if a designer sees that a particular flip-flop has a hold time violation, the designer may insert a generic buffer at the input pin to the flip-flop, thereby delaying the incoming signal relative to the clock input. However, that flip-flop may be a common end point for paths with diverse start points. If a designer must sort through hundreds or even thousands of paths, the results may be that common end points are fixed repeatedly. Such repeated repair of a hold violation will often cause setup violations.
Improved methods and apparatus are therefore desired for fixing best case old time violations.